BUF_RD_ENABLE=Val_0x0, CMD_INHIBIT_DAT=Val_0x0, CMD_INHIBIT=Val_0x0, WR_XFER_ACTIVE=Val_0x0, IN_DORMANT_ST=Val_0x0, CMD_ISSUE_ERR=Val_0x0, DAT_LINE_ACTIVE=Val_0x0, CARD_STABLE=Val_0x0, CARD_DETECT_PIN_LEVEL=Val_0x0, BUF_WR_ENABLE=Val_0x0, SUB_CMD_STAT=Val_0x0, WR_PROTECT_SW_LVL=Val_0x0, CARD_INSERTED=Val_0x0, RD_XFER_ACTIVE=Val_0x0
Present State Register
| CMD_INHIBIT | Command Inhibit for CMD line This bit indicates the following: SD or eMMC mode: If this bit is set to 0x0, it indicates that the CMD line is not in use and the Host controller can issue an SD or eMMC command using the CMD line. This bit is set when the SDMMC_CMD_R register is written. This bit is cleared when the command response is received. This bit is not cleared by the response of auto CMD12/23 but cleared by the response of read/write command. 0 (Val_0x0): Host Controller is ready to issue a command 1 (Val_0x1): Host Controller is not ready to issue a command |
| CMD_INHIBIT_DAT | Command Inhibit for DAT line This bit is applicable for both SD or eMMC modes and is generated if either DAT line active or Read transfer active is set to 0x1. If this bit is set to 0x0, it indicates that the Host Controller can issue subsequent SD or eMMC commands. 0 (Val_0x0): Can issue command which used DAT line 1 (Val_0x1): Cannot issue command which used DAT line |
| DAT_LINE_ACTIVE | DAT Line Active (SD or eMMC mode only). This bit indicates whether one of the DAT lines on the SD or eMMC bus is in use. In the case of read transactions, this bit indicates whether a read transfer is executing on the SD or eMMC bus. In the case of write transactions, this bit indicates whether a write transfer is executing on the SD or eMMC bus. For a command with busy, this status indicates whether the command executing busy is executing on an SD or eMMC bus. 0 (Val_0x0): DAT line inactive 1 (Val_0x1): DAT line active |
| DAT_7_4 | DAT[7-4] Line Signal Level. This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the SD_D[7-4] input (upper nibble) signals. |
| WR_XFER_ACTIVE | Write Transfer Active. This status indicates whether a write transfer is active for both SD or eMMC modes. 0 (Val_0x0): No valid data 1 (Val_0x1): Transferring data |
| RD_XFER_ACTIVE | Read Transfer Active. This bit indicates whether a read transfer is active for both SD or eMMC modes. 0 (Val_0x0): No valid data 1 (Val_0x1): Transferring data |
| BUF_WR_ENABLE | Buffer Write Enable. This bit is used for non-DMA transfers. This bit is set if space is available for writing data. 0 (Val_0x0): Write disable 1 (Val_0x1): Write enable |
| BUF_RD_ENABLE | Buffer Read Enable. This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. 0 (Val_0x0): Read disable 1 (Val_0x1): Read enable |
| CARD_INSERTED | Card Inserted. This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. 0 (Val_0x0): Reset, debouncing, or no card 1 (Val_0x1): Card inserted |
| CARD_STABLE | Card Stable. This bit indicates the stability of the Card Detect Pin Level (see CARD_DETECT_PIN_LEVEL bit). A card is not detected if this bit is set to 0x1 and the value of the CARD_INSERTED bit is 0x0. 0 (Val_0x0): Reset or debouncing 1 (Val_0x1): No card or Inserted |
| CARD_DETECT_PIN_LEVEL | Card Detect Pin Level. This bit reflects the inverse synchronized value of the card detect signal. 0 (Val_0x0): No card present 1 (Val_0x1): Card present |
| WR_PROTECT_SW_LVL | Write Protect Switch Pin Level. This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card write protect signal. 0 (Val_0x0): Write protected 1 (Val_0x1): Write enabled |
| DAT_3_0 | DAT[3-0] Line Signal Level. This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the SD_D[0-3] input (lower nibble) signals. |
| CMD_LINE_LVL | Command-Line Signal Level. This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the SD_CMD input signal. |
| CMD_ISSUE_ERR | Command Not Issued by Error. This bit is set if a command cannot be issued after setting the SDMMC_CMD_R register due to an error except the Auto CMD12 error. 0 (Val_0x0): No error for issuing a command 1 (Val_0x1): Command cannot be issued |
| SUB_CMD_STAT | Sub-command Status. This bit is used to distinguish between a main command and a Sub-command status. 0 (Val_0x0): Main command status 1 (Val_0x1): Sub-command status |
| IN_DORMANT_ST | In Dormant Status. for both SD or eMMC modes, this bit always returns 0x0. 0 (Val_0x0): Not in Dormant state 1 (Val_0x1): In Dormant state |